module dds_ip_tb();

    reg clk;

    initial begin
        clk = 1'b0;
        forever #50 clk = ~clk;
    end

    dds_ip u_dds_ip
    (
        .clk(clk),
        .dds_m_axis_data_tdata(),
        .dds_m_axis_data_tvalid()
    );


endmodule